Hello Live !

Jan

地球那边的月亮圆吗?

到美帝三个月了，一个学期结束，趁还记得点什么赶紧把感受都记下。一是留作备份，二是可供大家参考，少走弯路。

总体来说，我从交大参加交换项目出国的流程大体是这样的。

收到交换项目的报名通知（我们这届，理学院是孙维敏老师在负责）
在明大的网站上提交申请
准备出国要用的相关材料
- 大学本科已经有的成绩（在交大办理）
- 下学期在交大的选课的清单（在交大办理）
- 高考成绩（去交大档案馆办理）
- 托福成绩（回家过年的时候顺便准备托福）
明大邮件通知录取结果
- 可以考虑买机票
申请留学签证（具体过程请参照这里）
- 搞定护照先（具体过程请看这里）
- 跟明大有关的材料
  - 明大给你的通知书
  - 明大跟你的邮件往来
- 跟交大有关的材料
  - 在交大的成绩
  - 交大跟明大的协议
- 跟自己有关的材料
  - 英语能力证明
  - 财力证明
  - 学习能力证明
  - 亲属的相关证明等
放暑假，跟好朋友们聚一聚，准备出国用的行李等各种杂物
到美国，找房子
到明大报道，参加各种入学前的培训
上课

总而言之，语言 + 签证
Read more

Mar

Quick tutorial to GNU make

The idea for this post comes from this thread (How did you learn the GNU make tool) from StackOverflow.

The GNU make command will look for a file named makefile by default.

Makefile is just a set of rules. If you offer options for make to build, then make will go to that rule to build according to the rules corresponds to the rules you give it. If you do not offer make any option, then make will go with its default option which is identical to the option all.

For simple projects like projects with one or two files. The following makefile is already good enough.

all:
gcc foo.c – o foo

We can also have different rules for different object files (files with .o extension), like the following.

all:
     gcc -c foo.c
     gcc -c bar.c
     gcc foo.o bar.o -o app

There is a problem as we add more files in to projects because the we need to type in the name for each one of them. Make will compile and link everyone of them every time you invoke make command. This way, it will do some unnecessary work.

Make knows how to save this extra work if makefile tells make which object file depends on which source file. With this dependency assumed, make will compare the time stamp of source file and object file. If the source is no newer than the object file, then make will not recompile the source file. Else if the source file is newer than the object file, then make will recompile the source file and link it the final executable.

An example makefile will be the following.

foo.o: foo.c
      gcc -c foo.c
bar.o: bar.c
      gcc -c bar.c
all:
      foo.o bar.o gcc foo.o bar.o -o app

Those text in red is the part tells make which source file some object file corresponds to. At this point the makefile is already in good shape and make will not do extra work when invoked. However, there is still some extra typing we need to do. In other words, for each object file, we need to create one specific rule to compile it, and add its name for “all” option. Fortunately, this extra work could be further saved.

Make will assume the dependency by default. So we can do the following thing.

OBJS=foo.o bar.o

app: $(OBJS)
gcc $(OBJS) -o app

all: app

This is almost the final version. The only problem for this is that we cannot change the flag, plus we may want to use anther command other than cc command to compile our code like gcc.

The final version is: