总而言之，语言 + 签证
The idea for this post comes from this thread (How did you learn the GNU make tool) from StackOverflow.
The GNU make command will look for a file named makefile by default.
Makefile is just a set of rules. If you offer options for make to build, then make will go to that rule to build according to the rules corresponds to the rules you give it. If you do not offer make any option, then make will go with its default option which is identical to the option all.
For simple projects like projects with one or two files. The following makefile is already good enough.
gcc foo.c – o foo
We can also have different rules for different object files (files with .o extension), like the following.
gcc -c foo.c
gcc -c bar.c
gcc foo.o bar.o -o app
There is a problem as we add more files in to projects because the we need to type in the name for each one of them. Make will compile and link everyone of them every time you invoke make command. This way, it will do some unnecessary work.
Make knows how to save this extra work if makefile tells make which object file depends on which source file. With this dependency assumed, make will compare the time stamp of source file and object file. If the source is no newer than the object file, then make will not recompile the source file. Else if the source file is newer than the object file, then make will recompile the source file and link it the final executable.
An example makefile will be the following.
gcc -c foo.c
gcc -c bar.c
foo.o bar.o gcc foo.o bar.o -o app
Those text in red is the part tells make which source file some object file corresponds to. At this point the makefile is already in good shape and make will not do extra work when invoked. However, there is still some extra typing we need to do. In other words, for each object file, we need to create one specific rule to compile it, and add its name for “all” option. Fortunately, this extra work could be further saved.
Make will assume the dependency by default. So we can do the following thing.
gcc $(OBJS) -o app
This is almost the final version. The only problem for this is that we cannot change the flag, plus we may want to use anther command other than cc command to compile our code like gcc.
The final version is:
$(CC) $(CFLAGS) $(OBJS) -o app
That is it, a quick introduction to GNU make command.
I have always wondered how the compiler works, after I have watched this video, I understood the overall process.
Processing: expand the macros
Compilation: from source code to assembly language
Assembly: from assembly language to machine code
Linking: create the final executable